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9d01d0884cdca7359b0ae2773c639f5574077ecb
AILang/bench
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Brummel 9d01d0884c iter ctt.2: Registry.type_def_module re-key to (owning_module, bare_name)
2026-05-12 22:23:46 +02:00
..
orchestrator-stats
iter ctt.2: Registry.type_def_module re-key to (owning_module, bare_name)
2026-05-12 22:23:46 +02:00
reference
iter ext-rename: .ailx → .ail across the live toolchain
2026-05-12 14:20:27 +02:00
architect_sweeps.sh
iter architect-iron-law.1: bench/architect_sweeps.sh runs the four design-md-consolidation sweeps against DESIGN.md
2026-05-10 20:01:47 +02:00
baseline_compile.json
audit 23: ratify compile_check baseline + DESIGN.md stub-fix
2026-05-12 00:57:12 +02:00
baseline_cross_lang.json
tidy: 21'g — resolve drift after 21'-arc close
2026-05-09 01:40:36 +02:00
baseline.json
tidy: 21'g — resolve drift after 21'-arc close
2026-05-09 01:40:36 +02:00
check.py
bench: regression harness — baseline.json + check.py
2026-05-09 00:36:06 +02:00
compile_check.py
tidy: 21'g — resolve drift after 21'-arc close
2026-05-09 01:40:36 +02:00
cross_lang.py
bench: 21'f — explicit-mode pair, full alloc+dec vs malloc+free
2026-05-09 01:21:15 +02:00
latency_harness.py
bench: latency_harness --runs N (stat-of-N, drop-slowest)
2026-05-08 15:17:53 +02:00
mono_dispatch.py
bench: mono-vs-vdisp micro-benchmark + revised Decision 11 rationale
2026-05-10 01:03:21 +02:00
run.sh
bench: 21'f — explicit-mode pair, full alloc+dec vs malloc+free
2026-05-09 01:21:15 +02:00
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