Brummel
ba516b8b39
Decision 9 ships. Through Iter 14e every ADT box, lambda env, and
closure pair was leaked. This iter substitutes GC_malloc for malloc
in all four IR allocation sites and links -lgc. No language change,
no AST change, no schema change.
Diff: 5 files modified, ~30 LOC net.
- codegen/lib.rs: 4 substitutions @malloc -> @GC_malloc.
- ail/main.rs: .arg("-lgc") in the clang invocation.
- 5 IR snapshot files: mechanical s/@malloc/@GC_malloc/, 9
occurrences. IR is bit-identical to pre-14f modulo this
substitution — exactly Decision 9's promise.
- e2e.rs: new test gc_handles_recursive_list_construction.
- examples/gc_stress.{ailx,ail.json}: new fixture, builds a 50-
element list via recursive Cons, sums it (1275).
Hash invariance verified: every existing fixture def hash
unchanged (codegen and link line are downstream of canonical
bytes; AST didn't move).
Tests 79 -> 80, all green. Existing 79 byte-identical stdout.
gc_stress -> 1275. list_map_poly -> 2/3/4 unchanged. sort
sorted-list unchanged. cargo doc 0 warnings.
GC notes (pertinent to future work):
- GC_INIT() not needed on Arch libgc 1.5.6 (auto-init via
__attribute__((constructor))).
- No conservative-scan over-retention observed.
- -lgc alone sufficient for link (pthread/dl transitive).
Pattern-shape note from gc_stress fixture writing: the post-14d
"if-then-else" replacement is `(match (app == n 0) (case
(pat-lit true) ...) (case (pat-wild) ...))`. Three lines for
what `if` used to do in one, but uniform with the language.
Worth flagging for the stdlib brief.
Language is feature-complete enough for stdlib. The three
blockers identified at the 14b boundary (redundancy 14d, tail
calls 14e, GC 14f) are all done. Plan 15a: first stdlib module
std_list.ailx with length/append/reverse/map/filter/fold_left/
fold_right/head/tail/is_empty.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
43 lines
1.1 KiB
LLVM
43 lines
1.1 KiB
LLVM
; AILang generated workspace; entry: ws_main
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source_filename = "ws_main.ail"
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target triple = "<NORMALIZED>"
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@.str_ws_main_fmt_int_0 = private unnamed_addr constant [6 x i8] c"%lld\0A\00", align 1
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declare i32 @printf(ptr, ...)
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declare i32 @puts(ptr)
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declare ptr @GC_malloc(i64)
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@ail_ws_lib_add_clos = private unnamed_addr constant { ptr, ptr } { ptr @ail_ws_lib_add_adapter, ptr null }
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@ail_ws_main_main_clos = private unnamed_addr constant { ptr, ptr } { ptr @ail_ws_main_main_adapter, ptr null }
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define i64 @ail_ws_lib_add(i64 %arg_a, i64 %arg_b) {
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entry:
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%v1 = add i64 %arg_a, %arg_b
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ret i64 %v1
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}
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define i64 @ail_ws_lib_add_adapter(ptr %_env, i64 %a0, i64 %a1) {
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entry:
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%r = call i64 @ail_ws_lib_add(i64 %a0, i64 %a1)
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ret i64 %r
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}
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define i8 @ail_ws_main_main() {
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entry:
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%v1 = call i64 @ail_ws_lib_add(i64 2, i64 3)
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call i32 (ptr, ...) @printf(ptr @.str_ws_main_fmt_int_0, i64 %v1)
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ret i8 0
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}
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define i8 @ail_ws_main_main_adapter(ptr %_env) {
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entry:
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%r = call i8 @ail_ws_main_main()
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ret i8 %r
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}
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define i32 @main() {
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call i8 @ail_ws_main_main()
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ret i32 0
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}
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