audit(cycle 316): drift disposition, bench seed docs + ratified re-pin, C29 scope paragraph

Cycle-close audit for the self-description cycle. Architect: drift_found (mild), core holds -- the gate is pure string shape in core imported by every seam (C28), the engine never evaluates description text (C17/inv 10), determinism pins untouched (C1); the store boundary is gated by construction with the raw write private; Op::Doc is a closed typed construct (C25). Regression: aura-bench green (exit 0) after one cycle-caused infra fix and one ratified re-pin. Infra fix: the bench campaign seeds (BP_SMA_A/B) predate C29 and were refused by the store gate (exit 2, infrastructure-first rule) -- both thread the authored sma_signal meaning line. Ratify: cli_fixed_cost's run_line_fnv moved because bench_sma_a.json now carries its doc -- the blueprint's content id shifts exactly as the spec anticipates for fixtures gaining docs; campaign result fingerprints are unchanged (descriptions stay out of execution, C29). Baselines re-pinned via aura-bench pin (throughput baselines re-pinned in the same sweep, all deltas within tolerance at pin time). Drift disposition: - [high] C29 guarantee overclaim vs emit/binding-column vocabularies -> contract now carries an explicit Scope paragraph naming the residue, tracked as #321 (also covers the [medium] non-roster schema walk gap). - [low] Delay's meaning line cited the stale C5 for the delay register; corrected to C9. refs #316, refs #321
2026-07-23 20:42:02 +02:00
parent 9c7f60b269
commit bd7585b609
8 changed files with 35 additions and 26 deletions
@@ -65,7 +65,7 @@ impl Delay {
                inputs: vec![PortSpec { kind: ScalarKind::F64, firing: Firing::Any, name: "series".into() }],
                output: vec![FieldSpec { name: "value".into(), kind: ScalarKind::F64 }],
                params: vec![ParamSpec { name: "lag".into(), kind: ScalarKind::I64 }],
-                doc: "emits the input from `lag` cycles ago — the explicit delay register (C5)",
+                doc: "emits the input from `lag` cycles ago — the explicit delay register (C9)",
            },
            |p| Box::new(Delay::new(p[0].i64() as usize)),
        )