feat(aura-core): name input ports

PortSpec gains a non-load-bearing `name: String`, so an input port is named just
as FieldSpec.name (output) and ParamSpec.name (param) already are — input ports
were the lone unnamed member of the node signature. Identity stays positional by
slot (C23); the name is render/debug only, never read by bootstrap or the run
loop. PortSpec drops Copy (String is not Copy), exactly as ParamSpec already does.

- Every aura-std node names its input slots: SMA/EMA "series", Sub/Add "lhs"/"rhs",
  Exposure "signal", SimBroker "exposure"/"price" (the slots become
  self-documenting), LinComb "term[i]" and Recorder "col[i]" generated in their
  build loops (mirroring LinComb's existing weights[i] param loop).
- derive_signature carries a composite's Role.name into the derived input port
  (it was dropped before — the output side already carried FieldSpec.name), so the
  graph model is homogeneously named at both levels.
- model_to_json (port_json + the composite-header inputs in scope_json) emits the
  name as a third tuple element: ["f64","any","exposure"]. The byte golden was
  re-captured (machine bytes) and its substring twins updated; the model is now
  fully named across inputs/outputs/params.
- All 16 PortSpec construction sites threaded in one compile-gate change; test
  fixtures carry fixture names. C8 realization note added to the design ledger.

Why name-only, no validation: the name is a pure debug symbol. Wire-by-name was
rejected (it would be a C23 contract change). Bootstrap slot-wiring validation
(which would close #21's same-kind swap footgun) is deferred to its own cycle —
a name alone does not catch the swap; it makes the slots self-documenting and
gives a future validation something to check against.

Verified: cargo test --workspace 168 green; clippy --all-targets -D warnings
clean; cargo build --workspace clean. Read-only render path (C9), no serde (C14),
scalar kinds unchanged (C4).

closes #50
refs #21
refs #51

crates/aura-std/src/sub.rs

@@ -24,8 +24,8 @@ impl Sub {
             "Sub",
             NodeSchema {
                 inputs: vec![
-                    PortSpec { kind: ScalarKind::F64, firing: Firing::Any },
-                    PortSpec { kind: ScalarKind::F64, firing: Firing::Any },
+                    PortSpec { kind: ScalarKind::F64, firing: Firing::Any, name: "lhs".into() },
+                    PortSpec { kind: ScalarKind::F64, firing: Firing::Any, name: "rhs".into() },
                 ],
                 output: vec![FieldSpec { name: "value", kind: ScalarKind::F64 }],
                 params: vec![],
@@ -82,4 +82,11 @@ mod tests {
         inputs[1].push(Scalar::F64(4.0)).unwrap();
         assert_eq!(sub.eval(Ctx::new(&inputs, Timestamp(0))), Some([Scalar::F64(6.0)].as_slice()));
     }
+
+    #[test]
+    fn input_slots_are_named_lhs_rhs() {
+        let s = Sub::builder();
+        let names: Vec<&str> = s.schema().inputs.iter().map(|p| p.name.as_str()).collect();
+        assert_eq!(names, ["lhs", "rhs"]);
+    }
 }