Fill the by-chance std vocabulary gaps: Div, Const source, Abs, pairwise Max/Min #236
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The rostered std vocabulary is exactly 23 zero-arg types (count-pinned, crates/aura-std/src/vocabulary.rs:10-18): Add/Sub/Mul/Sqrt/Scale, And/Gt/EqConst/Latch, SMA/EMA/Delay/RollingMax/RollingMin/Resample, Bias/LongOnly, FixedStop/PositionManagement/Sizer, ConstantCost/CarryCost/VolSlippageCost. Missing, with no implementation file anywhere in aura-std: Div, a Const source, Abs, pairwise Max/Min, a conditional/select node.
Consequence: RSI-class strategies (gain/loss split + ratio) are not composable from blueprint data — the shipped r_meanrev example works around the absence by folding constants into Scale factors and bound params. The gaps are by chance, not by design (settled 2026-07-07: operators missing from the std roster are built and rostered on demand; no design fork is involved).
Landed as
a0098fc(RED executable spec: an RSI-class gain/loss-split-and-ratio signal composed purely from blueprint data loads through std_vocabulary, builds, and runs to hand-computed RS values) +99237e1(GREEN: the five types rostered, count-pin 23 -> 28 in both the in-crate shape test and the CLI vocabulary e2e).Two micro-forks decided during authoring, both verified against existing structure: (1)
Constis a unary node with the constant as a bound f64 param, driven by a clock input whose value is ignored — a zero-input node never evaluates in the total-push engine, andEqConstalready establishes the constant-as-param-on-a-unary-node pattern; "source" in the issue title names the dataflow role, not an ingestion-boundarySourceimpl. (2)Divfollows IEEE-754 like the existingSqrt(x/0 -> signed inf, 0/0 -> NaN, unit-tested) — no error channel, matching the four-scalar hot-path contract.Max/Minare binary pairwise mirroringAdd/Sub, distinct from the windowedRollingMax/RollingMin;Absis unary mirroringSqrt.The conditional/select node the issue body mentions in passing is NOT part of this slice — it stayed out deliberately: its firing/gating semantics have real design surface (which input drives, what happens on a missing branch) and no acceptance box covered it. Both acceptance boxes are met on the branch. Closes via commit on merge.