Brummel
dd5c3fad96
Cycle 0003: aura-engine's first real content — a Sim that runs a wired DAG of
nodes deterministically, cycle by cycle. First point in the project where
authored nodes execute against data, not just under a hand-fed Ctx.
- `Sim` (aura-engine) — a bootstrapped, frozen root graph: a flat Vec<NodeBox>
(each node owns its input columns, the cycle-0002 shape) + an index edge
table, topologically ordered (Kahn). `bootstrap` sizes every input column from
its node's schema, kind-checks each edge and source target, and rejects
directed cycles — C7's "type check paid once at wiring" generalized to the
whole topology (`BootstrapError::{KindMismatch, BadIndex, Cycle}`).
- `run` — the deterministic loop: per record, forward the source value into its
target slots, evaluate nodes in topo order, capture the observed node's output
at eval time, and forward each `Some` output into its consumers' input columns
(a `None` forwards nothing — the structural seed of sample-and-hold). The loop
destructures `&mut self` into disjoint field borrows and allocates nothing on
the per-cycle path. This is the flat, monomorphized sharpening of RustAst's
reference-counted, interior-mutable observer push graph (C1/C7).
- `Edge` / `Target` (aura-engine) — producer->consumer and source->consumer wiring.
- `Sub` (aura-std) — a 2-input f64-difference node, so the loop is proven on a
real fan-out + join DAG (source -> {SMA(2), SMA(4)} -> Sub), with a determinism
assertion (C1: a second identical run is bit-identical).
Engine library depends only on aura-core; a test-only dev-dependency on aura-std
lets the integration test wire real Sma/Sub nodes. Sim carries a hand-written,
node-opaque `Debug` impl (Box<dyn Node> is not Debug; the impl prints
nodes.len() + the index/topology fields, needed by the bootstrap-rejection tests'
`unwrap_err`).
Deliberately deferred (recorded as decisions): freshness-gated recompute /
sample-and-hold (C5 -> cycle 0004, with the second source that makes it testable);
the explicit monotonic cycle_id counter (its first reader is freshness, 0004);
the Source trait + data-server ingestion + k-way merge (C3/C11); the builder API
(C19); the real sink + run registry (C18/C22).
Gates green: cargo build/test (26: 18 aura-core + 3 aura-std + 5 aura-engine)/
clippy -D warnings clean; surface-purity grep (no dyn-Any / Rc / RefCell) clean.
refs walking-skeleton
63 lines
1.7 KiB
Rust
63 lines
1.7 KiB
Rust
//! `Sub` — two-input f64 difference (input 0 minus input 1), e.g. a fast/slow
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//! spread. The walking skeleton's second worked node: it gives the sim loop a
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//! real fan-out + join to run (two SMAs joining into one node), exercising
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//! multi-input `Ctx` access inside a running graph.
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use aura_core::{Ctx, InputSpec, Node, NodeSchema, Scalar, ScalarKind};
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/// Two-input f64 difference: input 0 minus input 1. Emits `None` until both
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/// inputs have a value.
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#[derive(Default)]
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pub struct Sub;
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impl Sub {
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/// Build a `Sub` node.
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pub fn new() -> Self {
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Self
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}
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}
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impl Node for Sub {
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fn schema(&self) -> NodeSchema {
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NodeSchema {
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inputs: vec![
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InputSpec { kind: ScalarKind::F64, lookback: 1 },
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InputSpec { kind: ScalarKind::F64, lookback: 1 },
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],
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output: ScalarKind::F64,
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}
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}
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fn eval(&mut self, ctx: Ctx<'_>) -> Option<Scalar> {
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let a = ctx.f64_in(0);
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let b = ctx.f64_in(1);
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if a.is_empty() || b.is_empty() {
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return None;
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}
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Some(Scalar::F64(a[0] - b[0]))
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use aura_core::AnyColumn;
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#[test]
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fn sub_is_difference_once_both_inputs_present() {
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let mut sub = Sub::new();
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let mut inputs = vec![
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AnyColumn::with_capacity(ScalarKind::F64, 1),
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AnyColumn::with_capacity(ScalarKind::F64, 1),
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];
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// only input 0 present -> None
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inputs[0].push(Scalar::F64(10.0)).unwrap();
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assert_eq!(sub.eval(Ctx::new(&inputs)), None);
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// both present -> a - b
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inputs[1].push(Scalar::F64(4.0)).unwrap();
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assert_eq!(sub.eval(Ctx::new(&inputs)), Some(Scalar::F64(6.0)));
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}
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}
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