claude
40e962db89
First half of the #281 clock-enable set: Sign promotes the private sign0() semantics to vocabulary (strict comparisons; NaN and -0.0 fall to 0.0), Select is the stateless 2:1 mux that consumes Bool back into the F64 plane. Both zero-arg, Firing::Any, rostered (count pins 29→31); an engine E2E drives both through the real GraphBuilder→compile→run seam. refs #281
93 lines
4.8 KiB
Rust
93 lines
4.8 KiB
Rust
//! End-to-end coverage for the two new RTL standard cells (#281): `Select` (the
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//! Bool -> F64 conditional bridge) and `Sign` (the promoted `sign0()` semantics).
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//!
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//! The in-module tests in `aura-std/src/select.rs` and `aura-std/src/sign.rs`
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//! drive each node's `eval` directly — they never go through a `PrimitiveBuilder`
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//! schema, a `GraphBuilder`-resolved wiring, or a compiled+bootstrapped
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//! `FlatGraph`. That is the real seam a data-authored op-script or a Rust
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//! `sma_signal`-style builder exercises (C24), and it is exactly what this file
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//! proves: both cells are reachable from the public `aura_engine`/`aura_std`
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//! construction surface, wire cleanly by declared port name/kind, and produce
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//! the right values once actually driven cycle-by-cycle through a real
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//! `Harness::run`.
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use std::sync::mpsc;
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use aura_core::{Firing, Scalar, ScalarKind, Timestamp};
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use aura_engine::{GraphBuilder, VecSource};
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use aura_std::{Abs, Gt, Recorder, Select, Sign};
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/// A deterministic 5-tick F64 stream, no timestamps/randomness beyond a fixed
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/// literal sequence.
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fn ticks(values: &[f64]) -> Vec<(Timestamp, Scalar)> {
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values.iter().enumerate().map(|(i, &v)| (Timestamp(i as i64 + 1), Scalar::f64(v))).collect()
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}
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/// Property: **`Select` is the real Bool -> F64 bridge, through the compiled
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/// engine, not merely by direct `eval`.** One `price` source feeds both `Abs`
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/// (computing `|price|`) and `Gt(|price|, price)` (true exactly when
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/// `price < 0`); `Select(cond, then=price, otherwise=|price|)` must forward the
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/// RAW (possibly negative) `price` on the one row where `price < 0` and the
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/// (always non-negative) `|price|` on every other row. Since `|price| == price`
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/// for every non-negative row, the only way to distinguish "the mux correctly
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/// read `cond` and picked `then`" from "the wiring is inverted / stuck on one
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/// branch" is the single negative row: a stuck-on-`otherwise` bug would emit
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/// `3.0` there instead of `-3.0`. This drives the REAL `PrimitiveBuilder`
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/// schemas (`Gt`'s declared `bool` output, `Select`'s declared `bool`/`f64`/`f64`
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/// inputs) through `GraphBuilder::build` -> `compile_with_params` ->
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/// `Harness::run`, the seam an op-script or a `sma_signal`-style Rust builder
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/// actually uses — the in-module `select.rs` unit tests never leave direct
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/// `eval` calls.
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#[test]
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fn select_bridges_a_real_gt_bool_output_into_f64_end_to_end() {
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let (tx, rx) = mpsc::channel();
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let mut g = GraphBuilder::new("root");
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let price = g.source_role("price", ScalarKind::F64);
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let abs = g.add(Abs::builder());
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let gt = g.add(Gt::builder());
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let select = g.add(Select::builder());
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let rec = g.add(Recorder::builder(vec![ScalarKind::F64], Firing::Any, tx));
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g.feed(price, [abs.input("value"), gt.input("b"), select.input("then")]);
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g.connect(abs.output("value"), gt.input("a"));
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g.connect(abs.output("value"), select.input("otherwise"));
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g.connect(gt.output("value"), select.input("cond"));
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g.connect(select.output("value"), rec.input("col[0]"));
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let mut h = g.build().expect("resolves by name").bootstrap_with_params(vec![]).expect("bootstraps");
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h.run(vec![Box::new(VecSource::new(ticks(&[-3.0, 0.0, 2.0, -0.0, 5.0])))]);
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let trace: Vec<f64> = rx.try_iter().map(|(_, row)| row[0].as_f64()).collect();
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assert_eq!(
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trace,
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vec![-3.0, 0.0, 2.0, 0.0, 5.0],
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"row 0 (price<0) must forward the raw negative `then`; every other row forwards `|price|`"
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);
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}
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/// Property: **`Sign` correctly registers its `PrimitiveBuilder` schema
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/// (F64 in, F64 out) and dispatches through a compiled+bootstrapped
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/// `FlatGraph`, mapping the three sign regions across real engine cycles** —
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/// not merely via a direct `eval` call (the in-module `sign.rs` unit tests'
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/// seam). A schema/wiring regression (wrong port kind, wrong output arity)
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/// would fail at `GraphBuilder::build` or `compile_with_params`, before a
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/// single cycle runs; a dispatch regression would show up in the recorded
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/// values below.
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#[test]
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fn sign_dispatches_through_a_compiled_graph_across_all_three_regions() {
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let (tx, rx) = mpsc::channel();
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let mut g = GraphBuilder::new("root");
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let spread = g.source_role("spread", ScalarKind::F64);
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let sign = g.add(Sign::builder());
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let rec = g.add(Recorder::builder(vec![ScalarKind::F64], Firing::Any, tx));
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g.feed(spread, [sign.input("value")]);
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g.connect(sign.output("value"), rec.input("col[0]"));
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let mut h = g.build().expect("resolves by name").bootstrap_with_params(vec![]).expect("bootstraps");
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h.run(vec![Box::new(VecSource::new(ticks(&[-3.0, 0.0, 2.5, -0.0, 4.0])))]);
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let trace: Vec<f64> = rx.try_iter().map(|(_, row)| row[0].as_f64()).collect();
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assert_eq!(trace, vec![-1.0, 0.0, 1.0, 0.0, 1.0], "all three sign regions, dispatched through the real engine");
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}
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