claude
a32dc38d18
C29 compile/unit seam, task 3 of the self-description plan: every aura-std NodeSchema literal threads its one-line doc. Four texts were corrected against the actual eval/finalize semantics rather than taken from the plan table verbatim: Delay is a lag-N register (not one-step), GatedRecorder flushes an ungated final row at finalize, Latch is a level-sensitive set/reset register (captures no input), SeriesReducer emits its single summary row at finalize (not per cycle). Gate: cargo build -p aura-std --lib clean; full std test run follows at the all-crates gate once strategy/backtest/engine thread their sites (the earlier per-crate test gate was unsatisfiable in isolation -- std's dev-deps pull crates whose sites belong to later tasks). refs #316
103 lines
3.3 KiB
Rust
103 lines
3.3 KiB
Rust
//! `Add` — two-input f64 sum (input 0 plus input 1), the companion to `Sub`.
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//! Combines two signal streams into one — the most basic combinator for the
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//! north-star "combine one signal with another" research move (C10).
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use aura_core::{Cell, Ctx, FieldSpec, Firing, Node, NodeSchema, PortSpec, PrimitiveBuilder, ScalarKind};
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/// Two-input f64 sum: input 0 plus input 1. Emits `None` until both inputs
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/// have a value.
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///
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/// # Firing and warm-up
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///
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/// Both inputs are [`Firing::Any`](aura_core::Firing::Any) — a *mode-A as-of
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/// join*: the node fires on every cycle in which either leg is fresh (once both
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/// have produced a value), pairing the fresh leg with the held value of the
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/// other. Until both legs have a value it emits `None` (no cold-leg-as-`0.0`).
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/// With heterogeneous sources sharing a timestamp (same `ts` from two sources =
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/// two distinct cycles, C4), a fired node emits one row per *cycle*, so a
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/// recorded combined stream may carry more than one row per timestamp.
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pub struct Add {
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out: [Cell; 1],
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}
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impl Add {
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/// Build an `Add` node.
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pub fn new() -> Self {
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Self { out: [Cell::from_f64(0.0)] }
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}
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/// The param-generic recipe for a blueprint primitive: paramless, builds through
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/// `Add::new`.
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pub fn builder() -> PrimitiveBuilder {
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PrimitiveBuilder::new(
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"Add",
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NodeSchema {
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inputs: vec![
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PortSpec { kind: ScalarKind::F64, firing: Firing::Any, name: "lhs".into() },
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PortSpec { kind: ScalarKind::F64, firing: Firing::Any, name: "rhs".into() },
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],
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output: vec![FieldSpec { name: "value".into(), kind: ScalarKind::F64 }],
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params: vec![],
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doc: "elementwise sum of two input series",
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},
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|_| Box::new(Add::new()),
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)
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}
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}
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impl Default for Add {
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fn default() -> Self {
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Self::new()
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}
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}
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impl Node for Add {
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fn lookbacks(&self) -> Vec<usize> {
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vec![1, 1]
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}
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fn eval(&mut self, ctx: Ctx<'_>) -> Option<&[Cell]> {
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let a = ctx.f64_in(0);
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let b = ctx.f64_in(1);
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if a.is_empty() || b.is_empty() {
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return None;
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}
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self.out[0] = Cell::from_f64(a[0] + b[0]);
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Some(&self.out)
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}
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fn label(&self) -> String {
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"Add".to_string()
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use aura_core::{AnyColumn, Scalar, Timestamp};
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#[test]
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fn add_is_sum_once_both_inputs_present() {
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let mut add = Add::new();
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let mut inputs = vec![
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AnyColumn::with_capacity(ScalarKind::F64, 1),
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AnyColumn::with_capacity(ScalarKind::F64, 1),
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];
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// only input 0 present -> None
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inputs[0].push(Scalar::f64(10.0)).unwrap();
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assert_eq!(add.eval(Ctx::new(&inputs, Timestamp(0))), None);
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// both present -> a + b
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inputs[1].push(Scalar::f64(4.0)).unwrap();
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assert_eq!(add.eval(Ctx::new(&inputs, Timestamp(0))), Some([Cell::from_f64(14.0)].as_slice()));
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}
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#[test]
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fn input_slots_are_named_lhs_rhs() {
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let a = Add::builder();
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let names: Vec<&str> = a.schema().inputs.iter().map(|p| p.name.as_str()).collect();
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assert_eq!(names, ["lhs", "rhs"]);
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}
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}
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