Reject graphs with unwired or double-wired input ports — a wiring-totality check #65
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Reference: Brummel/Aura#65
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Today an interior node input slot left unwired runs a silent empty column at harness.rs around line 144, and two producers feeding one slot is structurally meaningless since one slot maps to one column, yet nothing compiles against it. This narrows the former names-as-load-bearing-wiring-keys issue, see the reconciliation comment, to one name-free structural check in validate_wiring at crates/aura-engine/src/blueprint.rs, called once from compile_with_params and recursive per nesting level so both the raw Composite::new path and the GraphBuilder build path inherit it. Rule: for every interior node, every declared input slot must be covered by exactly one wiring act — one Edge to+slot or one Role Target node+slot, counted uniformly. Zero coverage yields CompileError::UnconnectedPort with node and slot; more than one yields CompileError::DoubleWiredPort with node and slot. A composite own open input roles, source None, are coverage providers — the wired-by-enclosing boundary, with the root case already guarded by UnboundRootRole — not consumers. Index-based and name-free, so C23 is untouched. Out of scope: name-as-wiring-key promotion, node and port and field name uniqueness, per-port semantic tags, and any exposure and price swap-closure claim, subsumed by #64 or rejected as against C10 and C7.
Design reconciliation, eindampfen 2026-06-14: scope narrowed. The original goal — promote port and field names to load-bearing wiring keys and close the exposure and price swap structurally — is dropped. Rationale established in-context: #64, the typed-handle and named-port GraphBuilder at
a6a314b, already defused #21s silent integer-slot swap by moving authoring to handles plus visible port names; the residual symmetric same-kind swap is a valid-but-wrong name choice no structural check can catch; and a structural fix via per-port semantic tags would inject domain semantics into the deliberately domain-free engine, against C10 and C7. Node-name uniqueness, the earlier Option A, is also dropped — the builder wires by handle, not by node-name, so collisions never make wiring ambiguous. #65 is narrowed to a name-free wiring-totality check: every interior input slot must be covered by exactly one edge or one role target; zero coverage yields UnconnectedPort, more than one yields DoubleWiredPort, catching forgotten and doubled connections that today run a silent empty column. Provenance: user said eindampfen this session.Promote port/field names to load-bearing wiring keys to close the exposure/price swap structurallyto Reject graphs with unwired or double-wired input ports — a wiring-totality check