claude 40e962db89 feat(std): Sign and Select cells — the Bool→F64 bridge pair ...

First half of the #281 clock-enable set: Sign promotes the private
sign0() semantics to vocabulary (strict comparisons; NaN and -0.0
fall to 0.0), Select is the stateless 2:1 mux that consumes Bool
back into the F64 plane. Both zero-arg, Firing::Any, rostered
(count pins 29→31); an engine E2E drives both through the real
GraphBuilder→compile→run seam.

refs #281

2026-07-17 19:49:13 +02:00

..

abs.rs

feat(std): fill the by-chance vocabulary gaps — Const, Div, Abs, Max, Min

2026-07-10 19:59:10 +02:00

add.rs

refactor: Cell becomes the hot-path value carrier (C7/C8 realization)

2026-06-16 13:17:49 +02:00

and.rs

feat(aura-std): And — bool->bool conjunction

2026-06-17 16:57:15 +02:00

bias.rs

feat(stage1-r): bias rename + stop-rule + position-management + summarize_r (iter 1)

2026-06-23 19:48:58 +02:00

carry_cost.rs

feat(0085): per-cycle-held accrual — CarryCost + ChargeMode (approach B)

2026-06-29 01:00:51 +02:00

const_node.rs

feat(std): fill the by-chance vocabulary gaps — Const, Div, Abs, Max, Min

2026-07-10 19:59:10 +02:00

constant_cost.rs

feat(0083): CostNode trait + shared cost-record contract

2026-06-28 19:26:34 +02:00

cost_sum.rs

refactor(std,composites): interned cost[k].* port names — the leaks drop (#152)

2026-07-11 06:56:21 +02:00

cost.rs

refactor(std,composites): interned cost[k].* port names — the leaks drop (#152)

2026-07-11 06:56:21 +02:00

delay.rs

feat(aura-std): Delay — C5 lag-N register

2026-06-17 17:00:09 +02:00

div.rs

feat(std): fill the by-chance vocabulary gaps — Const, Div, Abs, Max, Min

2026-07-10 19:59:10 +02:00

ema.rs

refactor(aura-engine): Cell into the construction path — param-plane base/frontend split

2026-06-16 16:22:17 +02:00

eqconst.rs

feat(aura-std): EqConst — i64->bool equality gate

2026-06-17 16:44:11 +02:00

gated_recorder.rs

feat(0070): streaming sink reductions — finalize hook + folding sinks (#138)

2026-06-25 11:00:02 +02:00

gt.rs

feat(aura-std): Gt — strict f64->bool greater-than comparator

2026-06-17 16:55:19 +02:00

latch.rs

feat(stage1-r): bias rename + stop-rule + position-management + summarize_r (iter 1)

2026-06-23 19:48:58 +02:00

lib.rs

feat(std): Sign and Select cells — the Bool→F64 bridge pair

2026-07-17 19:49:13 +02:00

lincomb.rs

refactor(aura-engine): Cell into the construction path — param-plane base/frontend split

2026-06-16 16:22:17 +02:00

longonly.rs

feat(sweep-key): generic filesystem-portable member key + LongOnly bool node

2026-06-21 11:15:22 +02:00

max.rs

feat(std): fill the by-chance vocabulary gaps — Const, Div, Abs, Max, Min

2026-07-10 19:59:10 +02:00

min.rs

feat(std): fill the by-chance vocabulary gaps — Const, Div, Abs, Max, Min

2026-07-10 19:59:10 +02:00

mul.rs

feat(aura-std): add Mul + Sqrt primitives

2026-06-24 00:53:28 +02:00

position_management.rs

rename: retire the stage1-* family for the r-family (r-sma / r-breakout / r-meanrev)

2026-07-02 12:03:09 +02:00

recorder.rs

refactor(aura-ingest): fuse drain_trace taps via join_on_ts; doc the cadence rule

2026-06-18 15:02:11 +02:00

resample.rs

fix(std): snap time-bucket/session reads to the nominal minute

2026-07-17 18:49:27 +02:00

rolling_max.rs

feat(0071): stage1 breakout candidate — Donchian channel signal (#137)

2026-06-25 13:10:37 +02:00

rolling_min.rs

feat(0071): stage1 breakout candidate — Donchian channel signal (#137)

2026-06-25 13:10:37 +02:00

scale.rs

feat(std,cli): add the Scale node, retire the r-meanrev demo to data (#159 cut 3)

2026-07-07 22:02:50 +02:00

select.rs

feat(std): Sign and Select cells — the Bool→F64 bridge pair

2026-07-17 19:49:13 +02:00

series_reducer.rs

feat(0070): streaming sink reductions — finalize hook + folding sinks (#138)

2026-06-25 11:00:02 +02:00

session.rs

fix(std): snap time-bucket/session reads to the nominal minute

2026-07-17 18:49:27 +02:00

sign.rs

feat(std): Sign and Select cells — the Bool→F64 bridge pair

2026-07-17 19:49:13 +02:00

sim_broker.rs

feat(stage1-r): bias rename + stop-rule + position-management + summarize_r (iter 1)

2026-06-23 19:48:58 +02:00

sizer.rs

rename: retire the stage1-* family for the r-family (r-sma / r-breakout / r-meanrev)

2026-07-02 12:03:09 +02:00

sma.rs

feat(stage1-r): bias rename + stop-rule + position-management + summarize_r (iter 1)

2026-06-23 19:48:58 +02:00

sqrt.rs

feat(aura-std): add Mul + Sqrt primitives

2026-06-24 00:53:28 +02:00

stop_rule.rs

feat(std): VolTfStop — the timescale-matched volatility stop primitive

2026-07-14 02:08:28 +02:00

sub.rs

refactor: Cell becomes the hot-path value carrier (C7/C8 realization)

2026-06-16 13:17:49 +02:00

vocabulary.rs

feat(std): Sign and Select cells — the Bool→F64 bridge pair

2026-07-17 19:49:13 +02:00

vol_slippage_cost.rs

feat(0083): CostNode trait + shared cost-record contract

2026-06-28 19:26:34 +02:00

vol_tf_stop.rs

fix(std): snap time-bucket/session reads to the nominal minute

2026-07-17 18:49:27 +02:00